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dual, 14-bit, 80 msps/125 msps, serial lvds 1.8 v analog-to-digital converter data sheet AD9645 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2012 analog devices, inc. all rights reserved. features 1.8 v supply operation low power: 122 mw per channel at 125 msps with scalable power options snr = 74 dbfs (to nyquist) sfdr = 91 dbc at 70 mhz dnl = 0.65 lsb (typical); inl = 1.5 lsb (typical) serial lvds (ansi-644, default) and low power, reduced range option (similar to ieee 1596.3) 650 mhz full power analog bandwidth 2 v p-p input voltage range serial port control full chip and individual channel power-down modes flexible bit orientation built-in and custom digital test pattern generation clock divider programmable output clock and data alignment programmable output resolution standby mode applications communications diversity radio systems multimode digital receivers gsm, edge, w-cdma, lte, cdma2000, wimax, td-scdma i/q demodulation systems smart antenna systems broadband data applications battery-powered instruments handheld scope meters portable medical imaging and ultrasound radar/lidar general description the AD9645 is a dual, 14-bit, 80 msps/125 msps analog-to- digital converter (adc) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. the product operates at a conversion rate of up to 125 msps and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. the adc requires a single 1.8 v power supply and lvpecl-/ cmos-/lvds-compatible sample rate clock for full performance operation. no external reference or driver components are required for many applications. functional block diagram 10537-001 reference AD9645 14 vina+ a vdd drvdd 14 14 vinb+ vinb? d0a+ 14 d0b+ vina? vcm d1a+ d1b+ agnd d0a? d1a? d0b? d1b? dco+ dco? fco+ fco? 14-bit pipeline adc 14-bit pipeline adc pll, serializer and ddr lvds drivers serial port interface 1 to 8 clock divider sclk/ dfs sdio/ pdwn csb clk+ clk? figure 1. the adc automatically multiplies the sample rate clock for the appropriate lvds serial data rate. a data clock output (dco) for capturing data on the output and a frame clock output (fco) for signaling a new output byte are provided. individual channel power-down is supported; the AD9645 typically consumes less than 2 mw in the full power-down state. the adc provides several features designed to maximize flexibility and minimize system cost, such as programmable output clock and data align- ment and digital test pattern generation. the available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (spi). the AD9645 is available in a rohs-compliant, 32-lead lfcsp. it is specified over the industrial temperature range of ?40c to +85c. this product is protected by a u.s. patent. product highlights 1. small footprint. two adcs are contained in a small, space- saving package. 2. low power. the AD9645 uses 122 mw/channel at 125 msps with scalable power options. 3. pin compatibility with the ad9635 , a 12-bit dual adc. 4. ease of use. a data clock output (dco) operates at frequencies of up to 500 mhz and supports double data rate (ddr) operation. 5. user flexibility. spi control offers a wide range of flexible features to meet specific system requirements.
AD9645 data sheet rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dc specifications ......................................................................... 3 ac specifications .......................................................................... 4 di gital specifications ................................................................... 5 switching specifications .............................................................. 6 timing specifications .................................................................. 6 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 12 AD9645 - 80 .................................................................................. 12 AD9645 - 125 ................................................................................ 15 equivalent circuits ......................................................................... 18 theory of operation ...................................................................... 19 analog input considerations .................................................... 19 voltage reference ....................................................................... 20 clock input considerations ...................................................... 21 power dissipation and power - down mode ........................... 22 digital outputs and timing ..................................................... 23 output test modes ..................................................................... 26 serial port interface (spi) .............................................................. 27 configuration using the spi ..................................................... 27 hardware interface ..................................................................... 28 configuration without the spi ................................................ 28 spi accessible features .............................................................. 28 memory map .................................................................................. 29 reading the memory map register table ............................... 29 memory map register table ..................................................... 30 memory map register descriptions ........................................ 33 applications information .............................................................. 35 desi gn guidelines ...................................................................... 35 power and ground guidelines ................................................. 35 exposed pad thermal heat slug recommendations ............ 35 vcm ............................................................................................. 35 reference decoupling ................................................................ 35 spi port ........................................................................................ 35 outline dimensions ....................................................................... 36 ordering guide .......................................................................... 36 revision history 6/12 revision 0: initial version
data sheet AD9645 rev. 0 | page 3 of 36 specifications dc s pecifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?1.0 dbfs, unless otherwise noted. table 1. parameter 1 temp AD9645 - 80 AD9645 - 125 min typ max min typ max unit resolution 14 14 bits accuracy no missing codes full guaranteed guaranteed offset error full ? 0.6 ? 0. 2 + 0. 1 ? 0.6 ? 0. 2 + 0.2 % fsr offset matching full ? 0.2 + 0. 1 + 0.4 ? 0.2 + 0. 1 + 0.4 % fsr gain error full ? 4. 3 ? 1. 0 + 2.2 ? 5.1 ? 1. 5 + 2.3 % fsr gain matching full 0.5 2.2 0.6 2.6 % fsr dif ferential nonlinearity (dnl) full ? 0.6 + 1.3 ? 0.6 + 1.3 lsb 25c 0.65 0. 65 lsb integral nonlinearity (inl) full ? 2. 6 + 2. 8 ? 3.6 + 3.4 lsb 25c 1. 1 1.5 lsb temperature drift offset error full 2.7 3.3 ppm/ c internal voltage r eference output voltage (1 v mode) full 0.98 1.0 1.02 0.98 1.0 1.02 v load regulation at 1.0 ma (v ref = 1 v) 25c 2 2 mv input resistance 25c 7.5 7.5 k? input - referred noise v ref = 1.0 v 25c 0.9 5 1.0 lsb rms analog inpu ts differential input voltage (v ref = 1 v) full 2 2 v p -p common - mode voltage full 0.9 0.9 v common - mode range 25c 0 .5 1.3 0 .5 1.3 v differential input resistance 25c 5.2 5.2 k? differential input capacitance 25c 3.5 3.5 pf power supply avdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v i avdd 2 full 56 61 78 83 ma i drvdd (ansi - 644 mode) 2 full 48 50 57 60 ma i drvdd (reduced range mode) 2 25c 39 48 ma total power consumption dc input full 17 8 191 227 24 4 mw sine wave input ( two channels ; includes output drivers in ansi - 644 mode) full 18 7 200 24 3 25 7 mw sine wave input ( two channels ; includes output drivers in reduced range mode) 25c 171 2 27 mw power - down 25c 2 2 mw standby 3 full 92 10 1 115 12 6 mw 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions a nd for details on how these tests were completed. 2 measured with a low input frequency, full - scale sine wave on both channels. 3 can be controlled via the spi.
AD9645 data sheet rev. 0 | page 4 of 36 ac specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ? 1.0 dbfs, unless otherwise noted. ta ble 2. parameter 1 temp AD9645 - 80 AD9645 - 125 unit min typ max min typ max signal- to - noise ratio (snr) f in = 9.7 mhz 25c 75.6 75.2 dbfs f in = 30.5 mhz 25c 75.4 75. 0 dbfs f in = 70 mhz full 73.1 74. 5 72.8 74. 3 dbfs f in = 139. 5 mhz 25c 72. 1 72. 5 dbfs f in = 200 .5 mhz 25c 70. 0 70. 3 dbfs signal- to -noise- and - distortion ratio (sinad) f in = 9.7 mhz 25c 75. 6 75.1 dbfs f in = 30.5 mhz 25c 75.2 75.0 dbfs f in = 70 mhz full 72. 7 74. 4 72.4 74. 2 dbfs f in = 139. 5 mhz 25c 71.7 72. 4 dbfs f in = 200 .5 mhz 25c 69 .7 70.0 dbfs effective number of bits (enob) f in = 9.7 mhz 25c 12. 3 12.2 bits f in = 30.5 mhz 25c 12. 2 12. 2 bits f in = 70 mhz full 11.8 1 2.1 11.7 12. 0 b its f in = 139. 5 mhz 25c 11. 6 11. 7 bits f in = 200 .5 mhz 25c 11. 3 11. 3 bits spurious - free dynamic range (sfdr) f in = 9.7 mhz 25c 96 93 dbc f in = 30.5 mhz 25c 9 1 9 7 dbc f in = 70 mhz full 82 96 82 91 dbc f in = 139. 5 mhz 25 c 82 91 dbc f in = 200 .5 mhz 25c 82 81 dbc worst harmonic (second or third) f in = 9.7 mhz 25c ?96 ?93 dbc f in = 30.5 mhz 25c ?91 ?97 dbc f in = 70 mhz full ?96 ?83 ? 91 ? 82 dbc f in = 139. 5 mhz 25c ?82 ? 93 dbc f in = 200 .5 mhz 25c ?82 ?81 dbc worst other harmonic or spur f in = 9.7 mhz 25c ?99 ?96 dbc f in = 30.5 mhz 25c ?97 ?99 dbc f in = 70 mhz full ? 99 ? 8 2 ? 9 6 ? 84 dbc f in = 139. 5 mhz 25c ?93 ?91 dbc f in = 200 .5 mhz 25c ?91 ?87 dbc two - tone intermodulation distortion (imd) ain1 and ain2 = ?7.0 dbfs f in1 = 70.5 mhz, f in2 = 72.5 mhz 25c ? 93 ? 93 dbc crosstalk 2 25c ?97 ?97 db crosstalk (overrange condition) 3 25c ?97 ?97 db power supply rejection ratio (psrr) 4 avdd 25c 42 42 db drvdd 25c 67 67 db analog input bandwidth, full power 25c 650 650 mhz 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 crosstalk is measured at 70 mhz with ?1.0 dbfs analog input on one channel and no input on the adjacent channel. 3 overrange condition is specified with 3 db of the full - scale input range. 4 psrr is measured by injecting a sinusoidal signal at 10 mhz to the power supply pin and measuring the output spur on the fft. psrr is calculate d as the ratio of the amplitude of the spur voltage over the amplitud e of the pin voltage, expressed in decibels (db) .
data sheet AD9645 rev. 0 | page 5 of 36 digital specificatio ns avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?1.0 dbfs, unless otherwis e noted. table 3. parameter 1 temp min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl differential input voltage 2 full 0.2 3.6 v p -p input voltage range full agnd ? 0. 2 avdd + 0.2 v input comm on - mode voltage full 0.9 v input resistance (differential) 25c 15 k? input capacitance 25c 4 pf logic input ( sclk /dfs ) logic 1 voltage full 1.2 avdd + 0. 2 v logic 0 voltage full 0 0.8 v input resistance 25c 30 k? input capacitance 25c 2 pf logic input (csb) logic 1 voltage full 1.2 avdd + 0.2 v logic 0 voltage full 0 0.8 v input resistance 25c 26 k? input capacitance 25c 2 pf logic input (sdio /pdwn ) logic 1 voltage full 1.2 avdd + 0. 2 v logic 0 voltage full 0 0.8 v input resistance 25c 26 k? input capacitance 25c 5 pf logic output (sdio /pdwn ) 3 logic 1 voltage (i oh = 800 a) full 1.79 v logic 0 voltage (i ol = 50 a) full 0.05 v digital outputs (d 0x , d 1x ), ansi - 644 logic compl iance lvds differential output voltage magnitude (v od ) full 290 345 400 mv output offset voltage (v os ) full 1.15 1.25 1.35 v output coding (default) two s c omplement digital outputs ( d0x, d1x ), low power, reduced signal option logic compli ance lvds differential output voltage magnitude (v od ) full 160 200 230 mv output offset voltage (v os ) full 1.15 1.25 1.35 v output coding (default) twos c omplement 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 s pe cified for lvds and lvpecl only. 3 s pecified for 13 sdio/ pdwn pins sharing the same connection.
AD9645 data sheet rev. 0 | page 6 of 36 switching specificat ions avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input , 1.0 v internal reference, ain = ?1.0 dbfs, unless otherwise noted. table 4. parameter 1 , 2 temp min typ max unit clock 3 input clock rate full 10 1000 mhz conversion rate full 10 80/125 msps clock pulse width high (t eh ) full 6.25/4.00 ns clock pulse width low (t el ) full 6.25/4.00 ns output parameters 3 propagation delay (t pd ) full 2.3 ns rise time (t r ) (20% to 80%) full 300 ps fall time (t f ) (20% to 80%) full 300 ps fco propagation delay (t fco ) full 1.5 2.3 3.1 ns dco propagation delay (t cpd ) 4 full t fco + (t sample /1 6) ns dco to data delay (t data ) 4 full (t sample /1 6 ) ? 300 t sample /1 6 (t sample /1 6 ) + 300 ps dco to fco delay (t frame ) 4 full (t sample /1 6 ) ? 300 t sample /1 6 (t sample /1 6 ) + 300 ps lane delay (t ld ) 90 ps data -to - data skew (t data - max ? t data - min ) full 50 200 ps wake - up t ime (standby) 25c 250 ns wake - up time (power- down) 5 25c 375 s pipeline latency full 16 clock cycles aperture aperture delay (t a ) 25c 1 ns aperture uncertainty (jitter , t j ) 25c 1 74 f s rms out - of - range recovery time 25c 1 c lock cycles 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for detai ls on how these tests were completed. 2 measured on standard fr - 4 material. 3 can be adjusted via the spi. the conversion rate is the clock rate after the divider. 4 t sample /16 is based on the number of bits in two lvds data lanes. t sample = 1/f s . 5 wake - up time is defined as the time required to return to normal operation from power - down mode. timing specification s table 5 . parameter description limit unit spi timing requirements see figure 68 t ds setup time between the data and the rising edge of sclk 2 ns min t dh hold time bet ween the data and the rising edge of sclk 2 ns min t clk period of the sclk 40 ns min t s setup time between csb and sclk 2 ns min t h hold time between csb and sclk 2 ns min t high sclk pulse width high 10 ns min t low sclk pulse width low 10 ns min t en_ sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 68 ) 10 ns min t dis_sdio time required for the sdio pin to switch from an output to an input relativ e to the sclk rising edge (not shown in figure 68 ) 10 ns min
data sheet AD9645 rev. 0 | page 7 of 36 timing diagrams refer to the memory map register descriptions section and table 20 for spi register setti ngs. d0a? d0a+ d1a? d1a+ fco? bytewise mode fco+ d0a? d0a+ d1a? d1a+ fco? dco? dco+ dco+ clk+ vinx clk? dco? fco+ bitwise mode sdr ddr msb n ? 17 d12 n ? 17 d11 n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 msb n ? 16 d12 n ? 16 d11 n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 0 n ? 17 0 n ? 17 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 0 n ? 16 0 n ? 16 msb n ? 17 d11 n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 0 n ? 17 msb n ? 16 d11 n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 0 n ? 16 d12 n ? 17 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 0 n ? 17 d12 n ? 16 d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 0 n ? 16 t a t data t ld t eh t fco t frame t pd t cpd t el n ? 1 n n + 1 10537-002 figure 2 . 16 - bit ddr/sdr, two - lane, 1 frame mode (default) d0a? d0a+ d1a? d1a+ fco? bytewise mode fco+ d0a? d0a+ d1a? d1a+ fco? dco? dco+ dco+ clk+ clk? dco? fco+ bitwise mode sdr ddr 10537-003 d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 msb n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 msb n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 msb n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 msb n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 t eh t cpd t frame t fco t pd t data t ld t el vinx t a n ? 1 n n + 1 figure 3 . 12 - bit ddr/sdr, two - lane, 1 frame mode
AD9645 data sheet rev. 0 | page 8 of 36 d0a? d0a+ d1a? d1a+ fco? bytewise mode fco+ d0a? d0a+ d1a? d1a+ fco? dco? dco+ dco+ clk+ vinx clk? dco? fco+ bitwise mode sdr ddr msb n ? 17 d12 n ? 17 d11 n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 msb n ? 16 d12 n ? 16 d11 n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 0 n ? 17 0 n ? 17 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 0 n ? 16 0 n ? 16 msb n ? 17 d11 n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 0 n ? 17 msb n ? 16 d11 n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 0 n ? 16 d12 n ? 17 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 0 n ? 17 d12 n ? 16 d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 0 n ? 16 t a t data t ld t eh t fco t frame t pd t cpd t el n ? 1 n n + 1 10537-004 figure 4 . 16 - bit ddr/sdr, two - lane, 2 frame mode d0a? d0a+ d1a? d1a+ fco? bytewise mode fco+ d0a? d0a+ d1a? d1a+ fco? dco? dco+ dco+ clk+ clk? dco? fco+ bitwise mode sdr ddr 10537-005 d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 msb n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 msb n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 msb n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 msb n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 t eh t cpd t frame t fco t pd t data t ld t el vinx t a n ? 1 n n + 1 figure 5 . 12 - bit ddr/sdr, two - lane, 2 frame mode
data sheet AD9645 rev. 0 | page 9 of 36 d0x? d0x+ fco? dco+ clk+ vinx clk? dco? fco+ d12 n ? 17 msb n ? 17 d11 n ? 17 d10 n ? 17 d9 n ? 17 d8 n ? 17 d7 n ? 17 d6 n ? 17 d5 n ? 17 d4 n ? 17 d3 n ? 17 d2 n ? 17 d1 n ? 17 lsb n ? 17 0 n ? 17 0 n ? 17 msb n ? 16 d14 n ? 16 d13 n ? 16 t a t data t eh t fco t frame t pd t cpd t el n ? 1 n 10537-006 figure 6 . wordwise ddr, one- lane, 1 frame, 16 - bit output mode d0x? d0x+ fco? dco+ clk+ vinx clk? dco? fco+ d10 n ? 17 msb n ? 17 d9 n ? 17 d8 n ? 17 d7 n ? 17 d6 n ? 17 d5 n ? 17 d4 n ? 17 d3 n ? 17 d2 n ? 17 d1 n ? 17 d0 n ? 17 msb n ? 16 d10 n ? 16 t a t data t eh t fco t frame t pd t cpd t el n ? 1 n 10537-007 figure 7 . wordwise ddr, one- lane, 1 frame, 12 - bit output mode
AD9645 data sheet rev. 0 | page 10 of 36 abs olute maximum rating s table 6. parameter rating electrical avdd to agnd ? 0.3 v to +2.0 v drvdd to agnd ? 0.3 v to +2.0 v digital outputs to agnd (d0 x , d1 x , dco+, dco?, fco+, fco?) ? 0.3 v to +2.0 v clk+, clk? to agnd ? 0.3 v to +2.0 v vin x +, vin x? to agnd ? 0.3 v to +2.0 v sclk /d fs , sdio / pdwn , csb to agnd ? 0.3 v to +2.0 v rbias to agnd ? 0.3 v to +2.0 v vref to agnd ? 0.3 v to +2.0 v v cm to agnd ? 0.3 v to +2.0 v environmental operating temperature range (ambient) ? 40 c to +85 c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) ? 65c to +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stre ss rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance the exposed paddle i s the only ground connection on the chip. the exposed paddle must be soldered to the agnd plane of the users circuit board. soldering the exposed paddle to the users board also increases the relia bility of the solder joints and maximizes the thermal capability of the package. table 7 . thermal resistance package type airflow velocity (m/sec) ja 1, 2 jc 1, 3 jb 1, 4 jt 1, 2 unit 32- lead lfcsp , 5 mm 5 mm 0 37.1 3.1 20.7 0.3 c/w 1.0 32.4 0.5 c/w 2.5 29.1 0.8 c/w 1 per jedec jesd51 - 7, plus jedec jesd 51- 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). 3 per mil -s td 883, method 1012.1. 4 per jedec jesd51 - 8 (still air). typical ja i s specified for a 4 - layer pcb with a solid ground plane. as shown in table 7 , airflow improves heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, grou nd, and power planes reduces the ja . esd caution
data sheet AD9645 rev. 0 | page 11 of 36 pin configuration and function descripti ons 24 a vdd 23 rbias 22 vcm 21 vref 20 csb 19 dr vdd 18 d0a+ 17 d0a? 1 2 3 4 5 6 7 8 a vdd clk+ clk? sdio/pdwn sclk/dfs dr vdd d1b? d1b+ 9 10 11 12 13 14 15 16 d0b? d0b+ dco? dco+ fco? fco+ d1a? d1a+ 32 31 30 29 28 27 26 25 a vdd vinb? vinb+ a vdd a vdd vina+ vina? a vdd 10537-008 AD9645 top view (not to scale) notes 1. the exposed paddle is the only ground connection on the chip. it must be soldered to the analog ground of the pcb to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. figure 8 . pin configuration, top view table 8 . pin function descriptions pin no. mnemonic descriptio n 0 agnd, exposed pad the exposed paddle is the only ground connection on the chip. it must be soldered to the analog ground of the pcb to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 1, 24, 25, 28 , 29, 32 av dd 1.8 v supply pin s for adc analog core domain. 2, 3 clk+, clk ? differential encode clock for lv pecl, lvds, or 1.8 v cmos inputs. 4 sdio/pdwn data input/output in spi mode (sdio). bidirectional spi data i/o with 30 k ? internal pull - down. power - down in non - spi mode (pdwn). static control of chip power - down with 30 k ? i nternal pull - down. 5 sclk/dfs spi clock input in spi mode (sclk). 30 k ? i nternal pull - down. data format select in non - spi mode (dfs). stati c control of data output format with 30 k ? i nternal pull - down . dfs high = two s complement output; dfs low = offse t binary output. 6, 19 drvdd 1.8 v supply pins for output driver domain. 7, 8 d1b ?, d1b+ channel b digital outputs. 9, 10 d0b ?, d0b+ channel b digital outputs. 11, 12 dco ?, dco+ data clock outputs. 13, 14 fco ?, fco+ frame clock outputs. 15, 16 d1a ?, d1a+ channel a digital outputs. 17, 18 d0a ?, d0a+ channel a digital outputs. 20 csb s pi chip select. active low enable with 15 k ? i nternal pull - up. 21 vref 1.0 v voltage reference input/output. 22 vcm analog output voltage at mid avdd s upply. sets the common - mode voltage of the analog inputs. 23 rbias se ts the analog current b ias. connect this pin to a 10 k ? ( 1% tolerance) resistor to ground. 26, 27 vina?, vina+ channel a adc analog inputs. 30, 31 vinb+, vinb ? channel b adc analog inputs.
AD9645 data sheet rev. 0 | page 12 of 36 typical performance characte ristics AD9645 - 80 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 9.7mhz at ?1dbfs snr = 74.6db (75.6dbfs) sfdr = 95.2dbc 10537-009 figure 9 . single- tone 16k fft with f in = 9.7 mhz, f sample = 80 msps 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 30.5mhz at ?1dbfs snr = 74.3db (75.3dbfs) sfdr = 90.9dbc 10537-010 figure 10 . single - tone 16k fft with f in = 30.5 mh z , f sample = 80 msps 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 70.2mhz at ?1dbfs snr = 73.4db (74.4dbfs) sfdr = 95.3dbc 10537-0 11 figure 11 . single - tone 16k fft with f in = 70 .2 mhz, f sample = 80 msps 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 139.5mhz at ?1dbfs snr = 71db (72dbfs) sfdr = 80.8dbc 10537-012 figure 12 . single - tone 16k fft with f in = 139.5 mhz, f sample = 80 msps 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 200.5mhz at ?1dbfs snr = 68.9db (69.9dbfs) sfdr = 81.7dbc 10537-013 figure 13 . single - tone 16k fft with f in = 200 .5 mhz, f sample = 80 msps 0 ?15 ?30 ?45 ?60 ?75 ?105 ?90 ?120 ?135 0 84 12 16 28 20 24 32 4036 amplitude (dbfs) frequency (mhz) 10537-014 80msps 200.5mhz at ?1dbfs snr = 70.8db (71.8dbfs) sfdr = 81.5dbc figure 14 . single - tone 16k fft with f in = 200 .5 mhz, f sample = 80 msps , c lock d ivide = divide - by -8
data sheet AD9645 rev. 0 | page 13 of 36 120 ?20 ?90 0 snr/sfdr (dbfs/dbc) input amplitude (dbfs) 10537-015 sfdrfs sfdr snrfs snr 0 20 40 60 80 100 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 figure 15 . snr/sfdr vs. analog input level; f in = 9.7 mhz, f sample = 80 msp s 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 10537-016 ain1 and ain2 = ?7dbfs sfdr = 90.8dbc imd2 = ?94.2dbc imd3 = ?92.7dbc figure 16 . two - tone 16k fft with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 80 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?10 ?30 ?50 ?70 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) 10537-017 sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) figure 17 . two - tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 80 msps 110 0 0 260 snr/sfdr (dbfs/dbc) input frequency (mhz) 10537-018 70 10 20 30 40 50 60 80 90 100 100 120 140 80 20 40 60 240 160 180 200 220 sfdr snr figure 18 . snr/sfdr vs. f in ; f sample = 80 msps 120 0 ?40 ?20 0 20 40 60 80 snr/sfdr (dbfs/dbc) temperature (c) 10 20 30 40 50 60 70 80 90 100 110 10537-019 sfdr snr figure 19 . snr/sfdr vs. temperature; f in = 9.7 mhz, f sample = 80 msps 1.0 ?0.8 1 inl (lsb) output code 10537-020 ?0.6 ?0.4 ?0.2 0 0.4 0.2 0.6 0.8 1367 2733 4099 5465 6831 8197 9563 10929 12295 13661 15027 16393 figure 20 . inl; f in = 9.7 mhz, f sample = 80 msps
AD9645 data sheet rev. 0 | page 14 of 36 0.6 ?0.6 1 dnl (lsb) output code 10537-021 ?0.4 ?0.2 0 0.4 0.2 1367 2733 4099 5465 6831 8197 9563 10929 12295 13661 15027 16393 figure 21 . dnl; f in = 9.7 mhz, f sample = 80 msps 900,000 500,000 600,000 700,000 800,000 400,000 300,000 200,000 0 100,000 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n + 1 n + 2 n + 3 n + 4 n + 5 n number of hits code 0.95lsb rms 10537-022 figure 22 . input referred noise histogram; f sample = 80 msps 90 0 1 10 psrr (db) frequency (mhz) 10 20 30 40 50 60 70 80 avdd drvdd 10537-023 figure 23 . psrr vs. frequency; f clk = 125 mhz, f samp le = 80 msps 10537-024 110 0 10 50 30 70 90 snr/sfdr (dbfs/dbc) sample rate (msps) 10 20 30 40 60 50 70 90 80 100 sfdr snrfs figure 24 . snr/sfdr vs. sample rate ; f in = 9.7 mhz, f sample = 80 msps 10 50 30 70 90 snr/sfdr (dbfs/dbc) sample rate (msps) 10537-025 110 0 10 20 30 40 60 50 70 90 80 100 sfdr snrfs figure 25 . snr/sfdr vs. sample rate ; f in = 70 mhz, f sample = 80 msps
data sheet AD9645 rev. 0 | page 15 of 36 AD9645 - 125 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 20 30 40 50 60 amplitude (dbfs) frequency (mhz) 125msps 9.7mhz at ?1dbfs snr = 74.2db (75.2dbfs) sfdr = 93.7dbc 10537-026 figure 26 . single - tone 16k fft with f in = 9.7 mhz, f sample = 125 msps 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 amplitude (dbfs) frequency (mhz) 125msps 30.5mhz at ?1dbfs snr = 73.9db (74.9dbfs) sfdr = 96.8dbc 10537-027 figure 27 . single - tone 16k fft with f in = 30.5 mh z , f sample = 125 msps 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 amplitude (dbfs) frequency (mhz) 125msps 70.2mhz at ?1dbfs snr = 73.2db (74.2dbfs) sfdr = 92.1dbc 10537-028 figure 28 . single - tone 16k fft with f in = 70 .2 mhz, f samp le = 125 msps 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 amplitude (dbfs) frequency (mhz) 125msps 139.5mhz at ?1dbfs snr = 71.2db (72.2dbfs) sfdr = 90.7dbc 10537-029 figure 29 . single - tone 16k fft with f in = 1 39.5 mhz, f sample = 125 msps 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 amplitude (dbfs) frequency (mhz) 125msps 200.5mhz at ?1dbfs snr = 69.4db (70.4dbfs) sfdr = 81.5dbc 10537-030 figure 30 . single - tone 16k fft with f in = 200 .5 mhz, f sample = 125 msps 0 ?15 ?30 ?45 ?60 ?75 ?105 ?90 ?120 ?135 0 6 12 18 24 30 36 48 54 60 42 amplitude (dbfs) frequency (mhz) 10537-031 125msps 200.5mhz at ?1dbfs snr = 70.6db (71.6dbfs) sfdr = 81.3dbc figure 31 . single - tone 16k fft with f in = 200 .5 mhz, f sample = 125 msps , clock d ivide = divide - by -8
AD9645 data sheet rev. 0 | page 16 of 36 120 ?20 ?90 0 snr/sfdr (dbfs/dbc) input amplitude (dbfs) 10537-032 sfdrfs sfdr snrfs snr 0 20 40 60 80 100 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 figure 32 . snr/sfdr vs. analog input level; f in = 9.7 mhz, f sample = 125 msps 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 20 30 40 50 60 amplitude (dbfs) frequency (mhz) 10537-033 ain1 and ain2 = ?7dbfs sfdr = 89.6dbc imd2 = ?96.4dbc imd3 = ?90.8dbc figure 33 . two - tone 16k fft wi th f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?10 ?30 ?50 ?70 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) 10537-034 sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) figure 34 . two - tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 125 msps 110 0 0 260 snr/sfdr (dbfs/dbc) input frequency (mhz) 10537-035 70 10 20 30 40 50 60 80 90 100 100 120 140 80 20 40 60 240 160 180 200 220 sfdr snr figure 35 . snr/sfdr vs. f in ; f sample = 125 msps 120 0 ?40 ?20 0 20 40 60 80 snr/sfdr (dbfs/dbc) temperature (c) 10 20 30 40 50 60 70 80 90 100 110 snr sfdr 10537-071 figure 36 . snr/sfdr vs. temperature; f in = 9.7 mhz, f sample = 125 msps 1.5 ?1.5 1 inl (lsb) output code ?1.0 ?0.5 0 0.5 1.0 1367 2733 4099 5465 6831 8197 9563 10929 12295 13661 15027 16393 10537-072 figure 37 . inl; f in = 9.7 mhz, f sample = 125 msps
data sheet AD9645 rev. 0 | page 17 of 36 0.6 ?0.5 1 dnl (lsb) output code ?0.4 ?0.3 ?0.2 ?0.1 0 0.4 0.3 0.5 0.2 0.1 1367 2733 4099 5465 6831 8197 9563 10929 12295 13661 15027 16393 10537-073 figure 38 . dnl; f in = 9.7 mhz, f sample = 125 msps 900,000 500,000 600,000 700,000 800,000 400,000 300,000 200,000 0 100, 000 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n + 1 n + 2 n + 3 n + 4 n + 5 n number of hits code 1lsb rms 10537-076 figure 39 . input referred noise histogram; f sample = 125 msps 90 0 1 10 psrr (db) frequency (mhz) 10 20 30 40 50 60 70 80 avdd drvdd 10537-077 figure 40 . psrr vs. frequency; f clk = 125 mhz , f sample = 125 msps 110 0 10 20 30 40 60 50 70 90 80 100 10 50 30 70 90 130 110 snr/sfdr (dbfs/dbc) sample rate (msps) sfdr snrfs 10537-074 figure 41 . snr/sfdr vs. sample rate ; f in = 9.7 mhz , f sample = 125 msps 10537-075 110 0 10 20 30 40 60 50 70 90 80 100 10 50 30 70 90 130 110 snr/sfdr (dbfs/dbc) sample rate (msps) snrfs sfdr figure 42 . snr/sfdr vs. sample rate ; f in = 70 mhz , f sample = 125 msps
AD9645 data sheet rev. 0 | page 18 of 36 equivalent circuits a vdd vinx 10537-036 figure 43 . equivalent analog input circuit clk+ clk? 0.9v 15k? 10? 10? 15k? a vdd a vdd 10537-037 figure 44 . equivalent clock input circuit 31k? sdio/pdwn 400? dr vdd 10537-038 figure 45 . equivalent sdio/ pdwn input circuit dr vdd d0x?, d1x? d0x+, d1x+ v v v v 10537-039 figure 46 . equivalent digital output circuit 400? dr vdd 30k? sclk/dfs 10537-040 figure 47 . equivalent sclk /d fs input circuit rbias and vcm 400? a vdd 10537-041 figure 48 . equivalent rbias and vcm circuit csb 400? dr vdd 15k? 10537-042 figure 49 . equivalent csb input circuit vref a vdd 7.5k? 400? 10? 10537-043 figure 50 . equivalent vref circuit
data sheet AD9645 rev. 0 | page 19 of 36 theory of operation the AD9645 is a multistage, pipelined adc . each stage provides sufficient overlap to correct for flash errors in the preceding stage. the quantized outpu ts from each stage are combined into a final 14 - bit result in the digital correction logic. the serializer transmits this converted data in a 16 - bit output. the pipelined architecture permits the first stage to operate with a new input sample while the rem aining stages operate with preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched - capacitor dac and an interstage residue amplifier (for example, a multiplying digital - to - analog converter (mdac)). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to faci litate digital correction of flash errors. the last stage consists of a flash adc. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the data is then serialized and aligned to the frame and data clocks. a nalog input consider ations the analog input to the AD9645 is a differential switched - capacitor circuit designed for processing differential input signals. this circ uit can support a wide common - mode range while maintaining excellent performance. by using an input common - mode voltage of midsupply, users can minimize signal- dependent errors and achieve optimum performance. s s h c par c sample c sample c par vi nx? h s s h vi nx+ h 10537-044 figure 51 . switched - capacitor input circuit the clock signal alternately switches the input circuit between sample mode and hold mode (see figure 51 ). when the input circuit is switched to sample mode, the signal source must be capable of charg ing the sample capacitors and settling within one - half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. in addition, low q inductors or ferrite b eads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and , therefore , achieve the maximum bandwidth of the adc. such use of low q inductors or ferrite beads is required when driving the converter front end at high if frequencies. either a differential capacitor or two single - ended capacitors can be placed on the inputs to provide a matching passive network. this ultimately creates a low -pass filter at the input to limit unwanted broadband noise. see the an - 742 application note , the an - 827 application note , and the analog dialogue article transformer - coupled front - end for wideband a/d converters (volume 39, april 2005) for more information . in general, the precise values depend on the application. input common mode the analog inputs of the AD9645 are not internally dc - biased. therefore, in ac - coupled applications, the user must provide this bias externally. setting the device so that v cm = av dd /2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in figure 52 . 100 20 0.5 1.3 snr/sfdr (dbfs/dbc) input common mode (v) 30 40 50 60 70 80 90 0.6 0.7 0.8 0.9 1.0 1.1 1.2 sfdr snrfs 10537-078 figure 52 . snr/sfdr vs. input common - mode voltage, f in = 9.7 mhz, f sample = 125 msps an on - chip, comm on - mode voltage reference is included in the design and is available from the vcm pin. the vcm pin must be decoupled to ground by a 0.1 f capacitor, as described in the applications information section. maximum snr performance is achieved by setting the adc to the largest span in a differential configuration. in the case of the AD9645 , the largest input span available is 2 v p - p.
AD9645 data sheet rev. 0 | page 20 of 36 differe ntial input configurations there are several ways to drive the AD9645 either actively or passively. however, optimum performance is achieved by driving the analog i nput s differentially. using a d ifferential double balun configuration t o drive the AD9645 provides excellent perfor mance and a flexible interface to the adc for bas eband applications (see figure 55 ). for applications where snr is a key parameter, differential trans - former coupling is the recommended input configuration (see figure 56 ) because the noise pe rformance of most amplifiers is not adequate to achieve the true performance of the AD9645 . regardless of the configuration, the value of the shunt capacitor, c, i s dependent on the input frequency and may need to be reduced or removed. it is not recommended to drive the AD9645 input s single - ended. voltage reference a stable and accurate 1.0 v voltage reference is built into the AD9645 . the vref pin should be externally decoupled to ground with a low esr, 1.0 f capacitor in parallel w ith a low esr, 0.1 f ceramic capacitor. if the internal reference of the AD9645 is used to drive multiple converters to improve gain matching, the loading of the r eference by the other converters must be considered. figure 53 shows how the internal reference voltage is affected by loading. figure 54 shows the typical drift characteristics of the internal r eference in 1.0 v mode. the internal buffer generates the positive and negative full - scale references for the adc core. 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 ?4.5 ?5.0 0 3.0 2.5 2.0 1.5 1.0 0.5 v ref error (%) load current (ma) interna l v ref = 1v 10537-048 figure 53 . v ref error vs. load current 4 ?8 ?40 85 v ref error (mv) temperature (c) ?6 ?4 ?2 0 2 ?15 10 35 60 10537-049 figure 54 . typical v ref drift adc r 0.1f 0.1f 2v p-p vcm c *c1 *c1 c r 0.1f 0.1f 0.1f 33? 200? 33? 33? 33? vinx+ vinx? et1-1-i3 c c 5pf r *c1 is optional 10537-046 figure 55 . differential double balun input configuration for baseband applications 2v p-p r r *c1 *c1 is optional 49.9 0. 1f adt1-1wt 1:1 z ratio vinx? adc vinx+ *c1 c vcm 33? 33? 200? 0.1f 5pf 10537-047 figure 56 . differential transformer - coupled configuration for baseband applications
data sheet AD9645 rev. 0 | page 21 of 36 clock input consider ations for optimum perf ormance, clock the AD9645 sample clock inputs, clk+ and clk?, with a d ifferential signal. the signal is typically ac - coupled into the clk+ and clk? pins via a transformer or capacitors. th ese pins are biased internally (see figure 44 ) and require no external bias. clock inpu t options th e AD9645 has a flexible clock input structure. the clock in put can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal being used, clock source jitter is of the most concern, as described in the jitter considerations section. figure 57 and figure 58 show two preferred methods for clock ing th e AD9645 (at clock rates up to 1 ghz prior to the internal clock divider). a low jitter clock source is converted from a single - ended signal to a differential signa l using either an rf transformer or an rf balun. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clock input 50? 100? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1 z xfmr 10537-050 figure 57 . transformer - coupled differential clock (up to 200 mhz) 0.1f 0.1f 0.1f clock input 0.1f 50? clk? clk+ schottky diodes: hsms2822 adc 10537-051 figure 58 . balun - coupled differential clock (up to 1 ghz) the rf balun configuration is recommended for clock frequencies between 125 mhz and 1 ghz, and the rf transformer configu - ration is recom mended for clock frequencies from 10 mhz to 200 mhz. the back - to - back schottky diodes across the transformer/balun secondary winding limit clock e xcursions into the AD9645 to approximately 0.8 v p - p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other por tions of the AD9645 while preserving the fast rise and fall times of the signal that are critical to achieving low jitter performance. however, the diode capacitanc e comes into play at frequencies above 500 mhz. care must be taken when choosing the appropriate signal limiting diode. if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins , as shown in figure 59 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 clock drivers offer excellent ji tter performance. 10 0? 0.1f 0.1f 0.1f 0.1f 240? 240? 50k? 50k? clk? clk+ clock input clock input adc ad951x pecl driver 10537-053 figure 59 . differential pecl sample clock (up to 1 ghz) a third option is to ac couple a differential lvds signal to the sample clock input pins, as shown in figure 60 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 clock drivers offer excellent jitter performance. 10 0? 0.1f 0.1f 0.1f 0.1f 50k? 50k? clk? clk+ adc clock input clock input ad951x lvds driver 10537-054 figure 60 . differentia l lvds sample clock (up to 1 ghz) in some applications, it may be acceptable to drive the sample clock inputs with a single - ended 1.8 v cmos signal. in such applica - tions, drive the clk+ pin directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f capacitor (see figure 61). optional 100? 0.1f 0.1f 0.1f 50? 1 1 50? resistor is optional. clk? clk+ adc v cc 1k? 1k? clock input ad951x cmos driver 10537-055 figure 61 . single - ended 1.8 v cmos input clock (up to 200 mhz ) input clock divider the AD9645 contains an input clock divider that can divide the input clock by integer values from 1 to 8. to achieve a given sample rate, the frequency of the externally applied clock must be multi - plied by th e divide value. the increased rate of the external clock normally results in lower clock jitter, which is beneficial for if undersampling applications.
AD9645 data sheet rev. 0 | page 22 of 36 clock duty cycle typical high speed adcs use both clock edges to generate a vari ety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the AD9645 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the perfor - mance of the AD9645 . noise and distortion performance are nearly flat for a wide range of duty cycles with the dcs on . jitter in the rising ed ge of the input is still of concern and is not easily reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates of less than 20 mhz, nominally. the loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f a ) due only to aperture jitter ( t j ) can be calculated by the following equation: snr degradation = 20 log 10 ? ? ? ? ? ? ? ? j a tf 2 1 in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if undersampling applications are particularly sensitive to jitter (see figure 62). 1 10 100 1000 16 bits 14 bits 12 bits 30 40 50 60 70 80 90 100 1 10 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps anal og i npu t f requ ency (mhz) 10 bits 8 bits rms clock jitter requirement snr (db) 10537-056 figure 62 . ideal snr vs. input frequency and jitter the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9645 . power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal - contr olled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock a s the last step. refer to the an- 501 application note and the an - 756 application note for more in - depth information about jitter performance as it r elates to adcs. power dissipation an d power - down mode as shown in figure 63, the power dissipated by the AD9645 is proportional to its sample rate. the AD9645 is placed in power - down mode either by the spi port or by asserting the pdwn pin high. in this state, the adc typically dissipates 2 mw. during power - down, the output drivers are placed in a high impedance state. asserting t he pdwn pin low returns the AD9645 to its normal operating mode. note that pdwn is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. 240 180 200 220 160 140 120 100 10 130 total power dissipation (mw) sample rate (msps) 30 50 70 90 110 50msps 80msps 125msps 40msps 20msps 65msps 105msps 10537-079 figure 63 . total power dissipation vs. f sample for f in = 9.7 mhz low power dissipation in power - down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capaci tors are discharged when the part enters power - down mode and must then be recharged when the part returns to normal operation. as a result, wake - up time is related to the time spent in power - down mode, and shorter power - down cycles result in proportionally shorter wake - up times. when using the spi port interface, the user can place the adc in power - down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake - up times are required. see the memory map section for more details on using these features.
data sheet AD9645 rev. 0 | page 23 of 36 digital outputs and timing the AD9645 differential outputs conform to the ansi - 644 lvds standard on default power - up. this default setting can be changed to a low power, reduced signal option (similar to the ieee 1596.3 standard) via the spi. the lvds driver current is derived on chip and sets t he output current at eac h output equal to a nominal 3.5 ma. a 100 ? differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing (or 700 mv p -p differential) at the receiver. when operating in reduced range mode, the output current is reduced to 2 ma. this results in a 200 mv sw ing (or 400 mv p - p differential) across a 100 ? termination at the receiver. the lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas for superior switching performance in noisy environments. single point - to - point net topologie s are recommended with a 100 ? termination resistor placed as close as possible to the receiver . if there is no far - end receiver termi - nation or there is poor differential trace routing, timing errors may result. to avoid such timing errors, ensure that th e trace length is less than 24 inches and that the differential output traces are close together and at equal lengths. figure 64 shows an example of the fco and data stream with proper trace length and position . d0 500mv/div d1 500mv/div dco 500mv/div fco 500mv/div 4ns/div 10537-058 figure 64 . AD9645 - 125 , lvds output timing example in ansi - 644 mode (default) figure 65 shows the lvds output timing example in reduced range mode. d0 400mv/div d1 400mv/div dco 400mv/div fco 400mv/div 4ns/div 10537-059 figure 65 . AD9645 - 125 , lvds output timing example in reduced range mode figure 66 shows a n example of the lvds output using the ansi - 644 standard (default) data eye and a time interval error (tie) jitter histogram with trace lengths of less than 24 inches on standard fr - 4 material . 6k 7k 1k 2k 3k 5k 4k 0 200ps 250ps 300ps 350ps 400ps 450ps 500ps tie jitter histogram (hits) 500 400 300 200 100 ?500 ?400 ?300 ?200 ?100 0 ?0.8ns ?0.4ns 0ns 0.4ns 0.8ns eye diagram voltage (mv) eye: all bits uls: 7000/400354 10537-060 figure 66 . data eye for lvds outputs in ansi - 644 mode with trace lengths of less than 24 inches on standard fr -4 m aterial, external 100 ? far - end termination only
AD9645 data sheet rev. 0 | page 24 of 36 figure 67 shows an example of trace lengths exceeding 24 inches o n standard fr - 4 material. note that the tie jitter histogram reflects the decrease of the data eye opening as the edge dev iates from the ideal position. 500 400 300 200 100 ?500 ?400 ?300 ?200 ?100 0 ?0.8ns ?0.4ns 0ns 0.4ns 0.8ns eye diagram voltage (mv) eye: all bits uls: 8000/414024 10k 12k 2k 4k 6k 8k 0 ?800ps ?600ps ?400ps ?200ps 0ps 200ps 400ps 600ps tie jitter histogram (hits) 10537-061 figure 67 . data eye for lvds outputs in ansi - 644 m ode with trace lengths greater t han 24 inches on standard fr - 4 material, external 100 ? far - end termination only it is the re spon sibility of the user to determine if the waveforms meet the timing budget of the design w hen the trace lengths exceed 24 inches. additional spi options allow the user to further increase the internal termination (increasing the current) of both outputs to drive longe r trace lengths. this increase in current can be achieved by programming register 0x15. although an increase in current produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the drvdd supply incre ases when this option is use d. the format of the output data is two s compl e ment by default. an example of the output coding format can be found in table 9 . to change the output data format to offset binary, see the memory map section. data from each adc is serialized and provided on a separate channel in two lanes in ddr mode . the data rate for each serial stream is equal to ( 16 bits the sample clock rate )/2 lanes, with a maximum of 1 g bps/lane [ (16 bits 125 msps )/( 2 lanes ) = 1 g bps /lane )]. the lowest typical conversion rate is 10 msps. for conversion rates of less than 20 msps , the spi must be used to reconfigure the integrated pll. see register 0x21 in the memory map section for details on enabling this feature. two output clocks are provided to assist in capturing data from the AD9645 . the dco is used to clock the output data and is equal to 4 the sample clock (clk) rate for the default mode of operation . data is clocked out of the AD9645 and must be captured on the rising and falling edges of the dco that supports double data rate (ddr) capturing. the fco is used to signal the start of a new output byte and is equal to the sample clock rate in 1 frame mode . see the timing diagrams section for more informati on. when the spi is used, the dco phase can be adjusted in 60 increments relative to the data edge. this enables the user to refine system timing margins , if required. the default dco+ and dco? timing, as shown in figure 2 , is 18 0 relative to the output data edge. a 12 - bit serial stream can also be initiated from the spi. this allows the user to implement and test compatibility to lower resolution systems. when changing the resolution to a 12 - bit serial stream, the data stream is shortened. see figure 3 for the 12- bit example. i n the default option with the serial output number of bits at 16, the data stream stuffs two 0s at the end of the 14 - bit serial data. in default mode, as shown in figure 2 , the msb is first in the data output serial stream. this can be inverted by using the spi so that the lsb is first in the data output serial stream. table 9 . digital output coding input (v) condition (v) o ffset binary output mode two s complement mode vin+ ? vin? +vref ? 0.5 lsb 11 11 1111 1111 1100 0111 1111 1111 11 00
data sheet AD9645 rev. 0 | page 25 of 36 table 10 . flexible output test modes output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data form at select notes 0000 off (default) n/a n/a n/a 0001 midscale short 1000 0000 0000 (12 - bit) 1000 0000 0000 0000 (1 6- bit) n/a yes offset binary code shown 0010 +full - scale short 1111 1111 1111 (12 - bit) 0000 0000 0000 0000 (1 6- bit) n/a yes offset binary c ode shown 0011 ? full - scale short 0000 0000 0000 (12 - bit) 0000 0000 0000 0000 (16 - bit) n/a yes offset binary code shown 0100 checkerboard 1010 1010 1010 (12 - bit) 1010 1010 1010 1010 (16 - bit) 0101 0101 0101 (12 - bit) 0101 0101 0101 010 0 (1 6- bit) no 0101 pn sequence long 1 n/a n/a yes pn23 itu 0 .150 x 23 + x 18 + 1 0110 pn sequence short 1 n/a n/a yes pn9 itu 0 .150 x 9 + x 5 + 1 0111 one - /zero - word toggle 1111 1111 1111 (12 - bit) 11 1 1111 1111 1100 ( 16- bit) 0000 0000 0000 (12 - bit) 0000 0000 0000 0000 (1 6- bit) no 1000 user input register 0x19 and register 0x1a register 0x1b and register 0x1c no 1001 1- /0 - bit toggle 1010 1010 1010 (12 - bit) 1010 1010 1010 10 0 0 ( 16 - bit) n/a no 1010 1 sync 0000 0011 1111 (12 - bit) 0000 0001 111 1 1100 ( 16 - bit) n/a no 1011 one bit high 1000 0000 0000 (12 - bit) 1000 0000 0000 0000 ( 16 - bit) n/a no pattern associated with the external pin 1100 mixed frequency 1010 0011 0011 (12 - bit) 1010 000 1 1001 1100 (1 6- bit) n/a no 1 all test mode options except pn sequence short and pn sequence long can support 12 - bit to 16 - bit word lengths to verify data capture to the receiver. there are 12 digital output test pattern optio ns available that can be initiated through the spi. this is a useful feature when validating receiver capture and timing. refer to table 10 for the output bit sequencing options available. some test patterns have two serial sequ ential words and can be alternated in various ways, depending on the test pattern chosen. note that some patterns do not adhere to the data format select option. in addition, custom user - defined test patterns can be assigned in the 0x19, 0x1a, 0x1b, and 0 x1c register addresses. the pn sequence short pattern produces a pseudorandom bit sequence that repeats itself every 2 9 ? 1 or 511 bits. a description of the pn sequence and how it is generated can be found in section 5.1 of the itu - t 0.150 (05/96) standard. the seed value is all 1s (see table 11 for the initial values). the output is a parall el representation of the serial pn9 sequence in msb - first format. the first output word is the first 14 bits of the pn9 sequence in msb aligned form. table 11 . pn sequence sequence initial value first three output samples (msb fi rst) , two s complement pn sequence short 0x1fe0 0x1df1, 0x3cc8, 0x294e pn sequence long 0x1fff 0x1fe0, 0x2001, 0x1c00 the pn sequence long pattern produces a pseudorandom bit sequence that repeats itself every 2 23 ? 1 or 8,388,607 bits. a description of the pn sequence and how it is generated can be found in section 5.6 of the itu - t 0.150 (05/96) standard. the seed value is all 1s (see table 11 for the initial values) and the AD9645 inverts the bit stream with relation to the itu standard. the output is a parallel representation of the serial pn23 sequence in msb - first format. the first output wo rd is the first 14 bits of the pn23 sequence in msb aligned form . consult the memory map section for information on how to change these additional digital output timing features through the spi.
AD9645 data sheet rev. 0 | page 26 of 36 sdio/ pdwn pin for applications t hat do not require spi mode operation, the csb pin is tied to drvdd , and the sdio/ pdwn pin controls power - down m ode according to table 12 . table 12. power - down mode pin settings pdwn pin voltage device m ode a gnd ( d efault) r un device, normal operation drvdd power down device note that in non - spi mode ( csb tied to dr vdd), the power - up sequence described in the power and ground g uidelines section must be adher ed to. violating t he power - up sequence necessitate s a soft reset via the sp i, which is not possible in non - spi mode. sclk/dfs pin the sclk/dfs pin is use d for output format selection in applications that do not require spi mode operation. this pin determines the digital out put format when the csb pin is held high during device power - up. when sclk/dfs is tied to dr vdd, the adc output format is two s c omplement ; w hen sclk/dfs is tied to a gnd , the adc output format is o ffs et b inary . table 13 . digital outp ut format d fs voltage output format agnd offset b inary drvdd twos c omplement csb pin the csb pin should be tied to dr vdd for applications that do not require spi mode operation. by tying csb high, all sclk and sdio information is ignored. note that , in non - spi mode ( csb tied to drvdd ), the power - up sequence described in the power and ground g uidelines section must be adhered to . violating the power - up sequence necessitate s a soft reset via spi, which is not possible in non - sp i mode. rbias pin to set the internal core bias current of the adc, place a 10.0 k ?, 1% tolerance resistor to ground at the rbias pin. output test modes the output test options are described in table 10 and are controlled by th e output test mode bits at address 0x0d. when an output test mode is enabled, the analog section of the adc is disconnected from the digital back - end blocks and the test pattern is run through the output formatting block. some of the test patterns are subj ect to output formatting, and some are not. the pn generators from the pn sequence tests can be reset by setting bit 4 or bit 5 of register 0x0d. these tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. for more information, see the an - 877 application note , interfacing to high speed adcs via spi .
data sheet AD9645 rev. 0 | page 27 of 36 serial port interface (spi) the AD9645 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi offers the user added flex ibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, which are docu - mented in the memory map section. for detailed operational information, see the an - 877 application note , interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk /dfs pin, the sdio /pdwn pin, and the csb pin (see table 14 ). sclk /dfs (a serial clock when csb is low ) is used to synchronize the read and write data pre sented from and to the adc. sdio /pdwn (serial data input/ output when csb is low ) is a dual - purpose pin that allows data to be sent to and read from the internal adc memory map registers. csb ( chip select bar ) is an active low control that enables or disables the spi read and write cycles. table 14 . serial port interface pins pin function sclk /dfs serial c lock when csb is low . the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio/pdwn serial d ata i nput/ o utput when csb is low . a dual - purpose pi n that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip s elect b ar. an active low control that enables the spi mode read and write cycles. the falling edge of csb , in conjunction with the rising edge of sclk /dfs , determines the start of the fram ing . an example of the serial timing is shown in figure 68 . see table 5 for definitions of the timing parameters . oth er modes involving the csb pin are available. csb can be held low indefinitely, which permanently enables the device; this is called streaming. csb can stall high between bytes to allow for additional external timing. when the csb pin is tied high, spi fun ctions are placed in high impedance mode. this mode turns on the secondary functions of the spi pin s. during the instruction phase of a spi operation , a 16 - bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and w1 bits. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on - chip memory. the first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. if the instruction is a readback operation, performing a readback causes the serial data input/ output (sdio) pin to ch ange direc tion from an input to an output at the appropriate point in the serial frame. all data is composed of 8 - bit words. data can be sent in msb - first mode or in lsb - first mode. msb - first mode is the default on power - up and can be changed via the spi port config uration register. for more information about this and other features, see the an - 877 application note , interfacing to high speed adcs via spi . don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 10537-062 figure 68 . serial port interface timing diagram
AD9645 data sheet rev. 0 | page 28 of 36 hardware interface the pins described in table 14 comprise the physical interface between the user programming device and the serial port of the AD9645 . the sclk /dfs pin and the csb pin function as inputs when using the spi interface. the sdio /pdwn pin is bidirec - tional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an - 812 application note , micro - controller - based serial port interface (spi) boot circu it . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk /dfs signal, the csb signal, and the sdio /pdwn signal are typically asynchronous to the adc clock, noise from these signal s can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9645 to pr event these signals from transi tioning at the converter inputs during critical sampling periods. the sclk /dfs and sdio /pdwn pins serve a dual function when the spi interface is not being used. when the pins are strapped to drvdd or ground during device pow er - on, they are associated with a specific function. table 12 and table 13 describe the strappable functions supported on the AD9645 . configuration without the spi in applications that do not interface to the spi control registers, the sclk/dfs pin and the sdio/ pdwn pin serve as standalone cmos - compatible control pins. when the device is powered up, it is assum ed that the user intends to use the pins as static control l ines for the output data format and power - down feature control. in this mode, csb should be connected to dr vdd, which disa bles the serial port interface. note that , in non - spi mode ( csb tied to dr vdd), the power - up sequence described in the power and ground g uidelines section must be adhered to . violating the power - up sequence necessitate s a soft reset via the spi, which is not possible in non - spi mode. spi accessible fe atures table 15 provides a brief description of the general features that are accessible via the spi. these features are described in detail in the an - 877 application note , interfaci ng to high speed adcs via spi . the AD9645 part - specific features are described in detail following table 16 , the external memory map reg ister table. table 15 . features accessible using the spi feature name description power mode allows the user to set either power - down mode or standby mode clock allows the user to access the dcs, set the clock divider, and set the clock divider phase offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set the output mode output phase allows the user to set th e output clock polarity adc resolution allows for power consumption scal ing with respect to sample rate
data sheet AD9645 rev. 0 | page 29 of 36 memory map reading the memory m ap register table each row in the memory map register table (see table 16 ) has eight b it locations . the memory map is roughly divided into three sections: the chip configuration registers (address 0x00 to address 0x02); the device index and transfer registers (address 0x05 and address 0xff) ; and the global adc function registers, including setup, control, and tes t (address 0x08 to address 0x102 ). the memory map register table lists the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x05, the device index register, has a hexadecimal default value of 0x3 3 . this means that in address 0x05, bits[7:6] = 00, bits [5 :4 ] = 1 1, bits[3:2] = 00 , and bits[ 1 :0] = 11 (in binary). this setting is the default channel index setting. the default value results in both adc channels receiving the next write command. for more information on this function and others, see the an - 877 application note , interfacing to high speed adcs via spi. this a pplication note details the functions controlled by register 0x00 to register 0xff. the remaining registers are documented in the memory map register descriptions section. open locations all address and bit locations that are no t included in table 16 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for exa mple, address 0x05). if the entire address location is open or not listed in table 16 (for example, address 0x13 ), this address location should not be written. default values after the AD9645 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table, table 16. logic levels an expl anation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. channel - specific registers som e channel setup functions, such as the signal monitor thresholds, can be programmed differently for each channel. in these cases, channel address locations are internally duplicated for each channel. these registers and bits are designated in table 16 as local. these local registers and bits can be accessed by setting the appropriate data channel bits (a or b) and the clock channel dco bit (bit 5) and fco bit (bit 4) in register 0x05. if all the bits are set, the subsequent write affects the registers of both channels and the dco/fco clock channels. in a read cycle, only one channel (a or b) should be set to read one of the t wo registers. if all the bits are set during a spi read cycle, the part returns the value for channel a. re gisters and bits that are designated as global in table 16 affect the entire part or the channel features for which independent settings are not allowed between channels. the settings in register 0x05 do not affect the global re gisters and bits.
AD9645 data sheet rev. 0 | page 30 of 36 m emory m ap r egister t able the AD9645 uses a 3- wire interface and 16 - bit addressing and , therefore , bit 0 and bit 7 in register 0x00 are set to 0, and bit 3 and bit 4 are set to 1. when bit 5 in register 0x00 is set high, the spi enter s a soft reset , where all of the user registers revert to their default values and bit 2 is automatically cleared. table 16. addr. (hex) pa rameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments chip configuration registers 0x00 spi port c onfiguration 0 = sdo active lsb f irst soft r eset 1 = 16 - bit address 1 = 16 - bit address soft r eset lsb f irst 0 = sdo active 0x18 n ibbles are mirrored to allow a given register value to perform the same function for eit her msb - first or lsb - first mode . 0x01 chip id (global) 8-b it c hip id , bits[ 7:0 ] AD9645 0x8 b = dual , 14- bit , 80 msps /125 msps , s er ial lvds 0x8 b unique chip id used to differentiate devices; read only. 0x02 chip grade (global) open speed grade id , bits [6:4] 100 = 80 msps 110 = 125 msps open open open open unique speed grade id used to differentiate grade d devices ; r ead only. device index and transfer registers 0x05 device index open open clock c hannel dco clock c hannel fco open open data channel b data channel a 0x33 bits are set to determine which device on chip receives the next write command. d efaul t is all devices on chip. 0xff transfer open open open open open open open initiate o verride 0x00 set r esolution/ s ample r ate o verride . global adc function registers 0x08 power modes (global) open open open open open open power mode 00 = chip run 01 = f ull power - down 10 = standby 11 = reset 0x00 determines various generic modes of chip operation. 0x09 clock (global) open open open open open open open duty cycle stabilize r 0 = off 1 = on 0x00 turns duty cycle stabilizer on or off. 0x0b clock d ivide (glo bal) open open open open open clock divide ratio [2:0] 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 0x0c enhancement control open open open open open c hop mode 0 = off 1 = on open open 0x00 enables/ disables chop mode.
data sheet AD9645 rev. 0 | page 31 of 36 addr. (hex) pa rameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments 0x0d test m ode (local except for pn sequence resets) user i nput t est m ode 00 = single 01 = alternate 10 = single once 11 = alternate once (a ffects user input test mode only , bits[3:0] = 1000 ) reset pn l ong g en reset pn s hort g en output test mode , bits[3:0] (local) 0000 = off (default) 0001 = midscale short 0010 = positive fs 0011 = negative fs 0100 = alternating checkerboard 0101 = pn23 sequence 0110 = pn 9 sequence 0111 = one - /zero - wor d toggle 1000 = user input 1001 = 1 - /0 - bit toggle 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency 0x00 when set, the test data is placed on the output pins in place of normal data . 0x10 offset a djust (local) 8 - bit device offset adjustment , b its [7:0] (local) offset adjust in lsbs from +127 to ?128 ( two s complement format) 0x00 device offset trim . 0x14 output mode open lvds - ansi/ lvds - ieee option 0 = lvds - ansi 1 = lvds -ieee reduced range link (global) ; see table 17 ope n open open output invert (local) open output format 0 = offset binary 1 = two s comple - ment (global) 0x01 configures the outputs and format of the data. 0x15 output adjust open open output driver termination , bits [1:0] 00 = none 01 = 200 ? 10 = 100 ? 11 = 100 ? open open open output drive 0 = 1 drive 1 = 2 drive 0x00 determines lvds or other output properties. 0x16 output phase open input clock phase adjust , bits [6:4] (value is number of input clock cycles of phase delay) ; see table 18 output clock phase adjust , bits [3:0] (0000 through 1011) ; see table 19 0x03 on devices using global clock divide, determines which phase of the divider output is used to supply the output clock. internal latching is unaffected. 0x18 v ref open open open open open internal v ref adjustment digital scheme , bits [2:0] 000 = 1.0 v p -p 001 = 1.14 v p -p 010 = 1.33 v p -p 011 = 1.6 v p -p 100 = 2.0 v p -p 0x04 select s and/or adjusts v ref . 0x19 user_patt1_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 1 lsb. 0x1a user_patt1_msb (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 1 msb. 0x1b user_patt2_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 2 lsb. 0x1c user_patt2_msb (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 2 msb.
AD9645 data sheet rev. 0 | page 32 of 36 addr. (hex) pa rameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments 0x21 serial output data control (global) lvds output 0 = m sb first (default) 1 = lsb first sdr/ddr one - lane/two - lane, bitwise/bytewise , bits [6:4] 000 = sdr two - lane, bitwise 001 = sdr two - la ne, bytewise 010 = ddr two - lane, bitwise 011 = ddr two - lane, bytewise (default) 100 = ddr one - lane , wordwise encode mode 0 = normal encode rate mode (default) 1 = l ow e ncode mode for sample rate of <20 msps 0 = 1 frame (default) 1 = 2 frame serial output number of bits 00 = 16 bits (default) 10 = 12 bits 0x30 serial stream control. sample rate of < 20 msps requires that bits[6:4] = 100 (ddr one - lane) and bit 3 = 1 (low encode mode) . 0x22 serial channel s tatus (local) open open open open open open chann el output reset channel power - down 0x00 used to powe r down individual sections of a converter. 0x100 resolution/ s ample rate override open resolution/ sample rate override enable resolution 01 = 14 bits 10 = 12 bits open sample rate 000 = 20 msps 001 = 40 msps 010 = 50 msps 011 = 65 msps 100 = 80 msps 101 = 105 msps 110 = 125 msps 0x00 resolution/ sample rate override (requires writing to the transfer register , 0xff). 0x101 user i/o control 2 open open open open open open open sdio pull - down 0x00 disables sdio pull - down. 0x102 user i/o control 3 open open open open vcm power - down open open open 0x00 vcm control.
data sheet AD9645 rev. 0 | page 33 of 36 memory map register descriptions for additional information about functions controlled in register 0x00 to register 0xff, see the an - 877 application note , interfacing to high speed adcs via spi . device index (register 0x05) there are certain features in the map that can be set inde pen - dently for each channel, whereas other features apply globally to all channels (depending on context) , regardless of which is selected. bits[1:0] in register 0x05 can be used to select which individual data channel is affected. the output clock channels can be selected in register 0x05 , as well. a smaller subset of the independent feature list can be applied to those devices. transfer (register 0xff) all registers except register 0x100 are updated the moment they are written. setting bit 0 of register 0xff high initializes the settings in the adc sample rate override re gister (address 0x100). power modes (register 0x08) bits2 open bits10 power mode in normal operation (bits[1:0] = 00), both adc channels are active. in power - down mode (bits[1:0] = 01), the digital datapath clocks are disabled while the digital datapath is reset. outputs are disabled. in standby mode (bits[1:0] = 10), the digital datapath clocks and the outputs are disabled. during a digital reset (bits[1:0] = 11), all the digital datapath clocks and the outputs (where applicable) on the chip are res et , except the spi port. note that the spi is always left under control of the user; that is, it is never automatically disabled or in reset (except by power - on reset). enhancement control (register 0x0c) bits3 open bit 2 chop mode for applications tha t are sensitive to offset voltages and other low frequency noise, such as homodyne or direct conversion receivers, chopping in the first stage of the AD9645 is a feature that can be enabled by setting bit 2. in the frequency domain, chopping translates offsets and other low frequency noise to f clk /2 , where it can be filtered. bits[1:0] open output mode (register 0x14) bit open bit 6 lvds - ansi/lvds - ieee opti on setting this bit select s the lvds - ieee (reduced range) option. the default setting is lvds - ansi. w hen lvds - ansi or the lvds - ieee reduced range link is selected, the user can select the driver t ermination (see table 17) . the dr iver current is automatically selected to give the proper output swing. table 17 . lvds - ansi/lvds- ieee options output mode, bit 6 output mode output driver termination output driver current 0 lvds - ansi user selectable automatically selected to give proper swing 1 lvds -ieee reduced range link user selectable automatically selected to give proper swing bits[5:3] open bit 2 output invert setting this bit inverts the output bit stream. bit 1 open bit 0 output format by default, this bi t is set to send the data output in two s complement format. clear ing this bit to 0 changes the output mode to offset binary. output adjust (register 0x15) bits6 open bits54 output driver termination these bits allow the user to select the internal t ermination resistor. bits[3:1] open bit 0 output drive bit 0 of the output adjust register controls the drive strength on the lvds driver of the fco and dco outputs only. the default va lues set the drive to 1, or the drive can be increased to 2 by settin g the appropriate channel bit in register 0x05 and then setting bit 0. these features cannot be used with the output driver termina tion select. the termination selection takes precedence over the 2 driver strength on fco and dco when both the output drive r termination and output drive are selected. output phase (register 0x16) bit open bits64 input clock phase adjust see table 18 for details. table 18 . input clock phase adjust options input clock phase adjust , bits [6:4] number of input clock cycles of phase delay 000 (default) 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
AD9645 data sheet rev. 0 | page 34 of 36 bits[3:0] output clock phase adjust see table 19 for details. table 19 . outp ut clock phase adjust options output clock (dco), phase adjust , bits [3:0] dco phase adjustment (degrees relative to d0x /d1x edge) 0000 0 0001 60 0010 120 0011 (default) 180 0100 240 0101 300 0110 360 0111 420 1000 480 1001 540 1010 600 1011 6 60 serial output data control (register 0x21) the serial output data control register is used to program the AD9645 in various output data modes , depending on the data capture solution. table 20 describes the various serialization options available in the AD9645 . resolution/ sample rate override (r egister 0x100) this register is designed to allow the user to downgrade the device. any attempt to upgrade the default speed grade results in a chip power - down. settings in this register are not initialized until bit 0 of the transfer register (register 0x ff) is written high. user i/o control 2 (register 0x101) bits[ 7 :1] open bit 0 sdio pull - down bit 0 can be set to disable the internal 30 k pull - down on the sdio pin, which can be used to limit the loading when many devices are connected to the spi bus. user i/o control 3 (register 0x102) bits[7:4] open bit 3 vcm power - down bit 3 can be set high t o power down the internal vcm generator. this feature is used when applying an external reference. bits[2:0] open table 20. spi register options serialization options selected register 0x21 contents serial output number of bits (sonb) frame mode serial data mode dco multiplier timing diagram 0x30 16- bit 1 ddr two - lane bytewise 4 f s see figure 2 (default setting) 0x20 16- bit 1 ddr two - lane bitwise 4 f s see figure 2 0x10 16- bit 1 sdr two - lane bytewise 8 f s see figure 2 0x00 16- bit 1 sdr two - lane bitwise 8 f s see figure 2 0x34 16- bit 2 ddr two - lane bytewise 4 f s see figure 4 0x24 16- bit 2 ddr two - lane bitwise 4 f s see figure 4 0x14 16- bit 2 sdr two - lane bytewise 8 f s see figure 4 0x04 16 - bit 2 sdr two - lane bitwise 8 f s see figure 4 0x40 16- bit 1 ddr one - lane wordwise 8 f s see figure 6 0x32 12- bit 1 ddr two - lane bytewise 3 f s see figure 3 0x22 12- bit 1 ddr two - lane bitwise 3 f s see figure 3 0x12 12- bit 1 sdr two - lane bytewise 6 f s see figure 3 0x02 12- bit 1 sdr two - lane bitwise 6 f s see figure 3 0x36 12- bit 2 ddr two - lane bytewise 3 f s see figure 5 0x26 12- bit 2 ddr two - lane bitwise 3 f s see figure 5 0x16 12- bit 2 sdr two - lane bytewise 6 f s see figure 5 0x06 12- bit 2 sdr two - lane bitwise 6 f s see figure 5 0x42 12- bit 1 ddr one - lane wordwise 6 f s see figure 7
data sheet AD9645 rev. 0 | page 35 of 36 applications information design guidelines before starting design and layout of the AD9645 as a system, it is recommended that the designer become familiar with these guidelines, which describe the special circuit connections and layout requirements that are needed for certain pins. power and ground g uidelines when connecting power to the AD9645 , it is recommended that two separate 1.8 v supplies be used. use one supply for analog (avdd); use a separate supply for the digital outputs (d rvdd). for both avdd and drvdd , se veral different decoupling capa citors should be used to cover both high and low frequencies. place these capacitors close to the point of entry at the pcb level and close to the pins of the part, with minimal trace length. if two supplies are used, avdd must not power up before drvdd. drvdd must power up before, or simultaneously with, avdd. if this sequence is violated, a soft reset via spi r egister 0x00 (bits[7:0] = 0x 3c) , follo wed by a digital reset via spi r egister 0x08 (bits[7:0] = 0x 03, then bits[7:0] = 0x00) , restore s the part to proper operation. in non - spi mode, the supply sequence is mandatory ; in this case , viola ting the supply sequence is non recoverable. a single pcb ground plane should be sufficient when using t he AD9645 . with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. exposed pad thermal heat slug recommendations it is required that the exposed pad on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and th ermal performance of the AD9645 . an exposed continuous copper plane on the pcb should mate to the AD9645 exposed pad, pin 0. the copper plane should have several v ias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be solder - filled or plugged. to maximize the coverage and adhesion between the adc and pcb, partition the continuous cop per plane by overlaying a silkscreen on the pcb into several uniform sections. this provides several tie points between the adc and pcb during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. see figure 69 for a pcb layout example. for detailed information on packaging and the pcb layout of chip scale packages, see the an - 772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) , at www.analog.com . silkscreen p artition pin 1 indic at or 10537-063 figure 69 . typical pcb layout vcm the vcm pin should be decoupled to ground with a 0.1 f capacitor. reference decoupling the vref pin should be extern ally decoupled to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. spi port the spi port sho uld not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - boar d spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9645 to prevent these signals from transitioning at the conve rter inputs during critical sampling periods.
AD9645 data sheet rev. 0 | page 36 of 36 outline dimensions 08-16-2010-b 1 0.50 bsc bottom view top view pin 1 indicator 32 9 16 17 24 25 8 exposed pad pin 1 indicator seating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min * 3.75 3.60 sq 3.55 * compliant to jedec standards mo-220-whhd-5 with exception to exposed pad dimension. figure 70 . 32 - lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp - 32 - 12) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9645 bcpz -80 ? 40c to +85c 32-l ead lead frame chip scale package (lfcsp_wq) cp -32-12 AD9645 bcpzrl7 - 80 ? 40c to +85c 32-l ead lead frame chip scale package (lfcsp_wq) cp -32-12 AD9645 bcpz -125 ? 40c to +85c 32-l ead lead frame chip scale package (lfcsp_wq) cp -32-12 a d9645 bcpzrl7 - 125 ? 40c to +85c 32-l ead lead frame chip scale package (lfcsp_wq) cp -32-12 AD9645 - 125ebz evaluation board 1 z = rohs compliant part. ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10537 -0- 6/12(0)

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